Increasing Pipelined IP Core Utilization in Process Networks Using Exploration

At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platforms, such as FPGAs, using IP cores to implement the data-path of the applications. A particular characteristic of the derived networks is the existence of selfloops. These selfloops have a large impact on the utilization of IP cores in the final hardware implementation of a PN, especially if the IP cores are deeply pipelined. In this paper, we present an exploration methodology that uses feedback provided by the Laura tool to increase the utilization of IP cores embedded in our PN network. Using this exploration, we go from 60MFlops to 1,7GFlops for the QR algorithm using the same number of resources except for memory.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
• Keywords: Chain Called Compaan/laura, FPL 2004, IP Cores, Leiden Embedded Research