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GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
14 years 3 months ago
VLSI CAD tool protection by birthmarking design solutions
Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern...
Lin Yuan, Gang Qu, Ankur Srivastava
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
14 years 3 months ago
Utilizing don't care states in SAT-based bounded sequential problems
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
Sean Safarpour, Görschwin Fey, Andreas G. Ven...
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
14 years 3 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
14 years 3 months ago
Interconnect capacitance extraction for system LCD circuits
This paper discusses interconnect capacitance extraction for system LCD circuits, where coupling capacitance is much significant since a ground plane locates far away unlike LSI ...
Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimot...
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
14 years 3 months ago
Thermal aware cell-based full-chip electromigration reliability analysis
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson