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HPCA
2004
IEEE
14 years 8 months ago
Signature Buffer: Bridging Performance Gap between Registers and Caches
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
Lu Peng, Jih-Kwon Peir, Konrad Lai
HPCA
2002
IEEE
14 years 8 months ago
Quantifying Load Stream Behavior
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
Suleyman Sair, Timothy Sherwood, Brad Calder
HPCA
2001
IEEE
14 years 8 months ago
Dynamic Branch Prediction with Perceptrons
This paper presents a new method for branch prediction. The key idea is to use one of the simplest possible neural networks, the perceptron as an alternative to the commonly used ...
Daniel A. Jiménez, Calvin Lin
HPCA
2001
IEEE
14 years 8 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
HPCA
2005
IEEE
14 years 1 months ago
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important, and this necessitates the development of ...
Krishnan Sundaresan, Nihar R. Mahapatra