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SIGARCH
2008
96views more  SIGARCH 2008»
13 years 8 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
ASPDAC
2000
ACM
102views Hardware» more  ASPDAC 2000»
14 years 1 months ago
A hybrid approach for core-based system-level power modeling
Reducing power consumption has become a key goal for systemon-a-chip (SOC) designs. Fast and accurate power estimation is needed early in the design process, since power reduction...
Tony Givargis, Frank Vahid, Jörg Henkel
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
14 years 1 months ago
HLS: combining statistical and symbolic simulation to guide microprocessor designs
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
Mark Oskin, Frederic T. Chong, Matthew K. Farrens
WSCG
2000
139views more  WSCG 2000»
13 years 10 months ago
Optimizing Combined Volume and Surface Data Ray Casting
Techniques for simultaneous display of volume data and geometric models have been reported in the literature. These techniques either require conversion from one representation to...
Marcelo Rodrigo Maciel Silva, Isabel Harb Manssour...
MSS
2007
IEEE
153views Hardware» more  MSS 2007»
14 years 2 months ago
Hybrid Host/Network Topologies for Massive Storage Clusters
The high demand for large scale storage capacity calls for the availability of massive storage solutions with high performance interconnects. Although cluster file systems are rap...
Asha Andrade, Ungzu Mun, Dong Hwan Chung, Alexande...