We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined a...
Current approaches to compute and exploit the flexibility of a component in an FSM network are all at the symbolic level [23, 30, 33, 31]. Conventionally, exploitation of this ï¬...
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...
A new technique for design centering, and for polytope approximation of the feasible region for a design are presented. In the rst phase, the feasible region is approximated by a ...
Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. K...