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ICCAD
1994
IEEE
112views Hardware» more  ICCAD 1994»
13 years 10 months ago
Selecting partial scan flip-flops for circuit partitioning
This paper presents a new method of selecting scan ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
Toshinobu Ono
ICCAD
1994
IEEE
110views Hardware» more  ICCAD 1994»
13 years 10 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
13 years 10 months ago
Multi-level network optimization for low power
This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
Sasan Iman, Massoud Pedram
ICCAD
1994
IEEE
90views Hardware» more  ICCAD 1994»
13 years 10 months ago
Algorithm selection: a quantitative computation-intensive optimization approach
Given a set of specifications for a targeted application, algorithm selection refers to choosing the most suitable algorithm for a given goal, among several functionally equivalen...
Miodrag Potkonjak, Jan M. Rabaey
ICCAD
1994
IEEE
111views Hardware» more  ICCAD 1994»
13 years 10 months ago
On modeling top-down VLSI design
We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept th...
Bernd Schürmann, Joachim Altmeyer, Martin Sch...