A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which fee...
Although numerous methods have been proposed for interconnect simulation, no single model exists for all kind of transmission line problems. This paper presents a new, single, gen...
While numerous power optimization techniques have been at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-el...
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditiona...
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...