Generation of BDDs from hardware algorithm descriptions

We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditional branches (if-then-else) and data dependent loops (while-end). Once BDDs are generated, we can immediately check the equivalence of two dierent algorithm descriptions just by comparing BDDs. This method can also be applied to verication between algorithm-level and gate-level designs. Another interesting application is to synthesize loop-free logic circuits from algorithm descriptions. We show the experimental results for some practical examples, such as Greatest Common Divisor (GCD) calculation. Although our method has a limitation in size of problems, it is very practical and useful for actual design verication.

• Type: Conference
• Year: 1996
• Where: ICCAD
• Authors: Shin-ichi Minato
• Keywords: Algorithm Descriptions, Hardware, Hardware Algorithm Descriptions, ICCAD 1996, Veri Cation