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ICCAD
1999
IEEE
98views Hardware» more  ICCAD 1999»
14 years 1 months ago
Buffer block planning for interconnect-driven floorplanning
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer inserti...
Jason Cong, Tianming Kong, David Zhigang Pan
ICCAD
1999
IEEE
67views Hardware» more  ICCAD 1999»
14 years 1 months ago
Realizable reduction for RC interconnect circuits
Interconnect reduction is an important step in the design and analysis of complex interconnects found in present-day integrated circuits. This paper presents techniques for obtain...
Anirudh Devgan, Peter R. O'Brien
ICCAD
1999
IEEE
81views Hardware» more  ICCAD 1999»
14 years 1 months ago
Robust optimization based backtrace method for analog circuits
In this paper, we propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. The proposed signal backtrace method is form...
Alfred V. Gomes, Abhijit Chatterjee
ICCAD
1999
IEEE
77views Hardware» more  ICCAD 1999»
14 years 1 months ago
Synthesis for multiple input wires replacement of a gate for wiring consideration
The alternative wire technique attempts to replace a target wire by another wire without changing the logic functionality. In this paper, we propose two new transformations of rep...
Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu
ICCAD
1999
IEEE
132views Hardware» more  ICCAD 1999»
14 years 1 months ago
The associative-skew clock routing problem
We introduce the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. The associative ...
Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelik...