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ICCAD
2004
IEEE
14 years 6 months ago
2004
IEEE
ICCAD
2004
IEEE
14 years 6 months ago
2004
IEEE
We demonstrate an algorithmfor interconnect modeling in rhe presence ofprocess variation based on extension of the truncated balanced realizationmodel reduction algorithmto multi-...
ICCAD
2004
IEEE
14 years 6 months ago
2004
IEEE
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended t...
ICCAD
2004
IEEE
14 years 6 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
ICCAD
2004
IEEE
14 years 6 months ago
2004
IEEE
Wirelength estimation is an important tool to guide the design optimization process in early design stages. In this paper, we present a novel wirelength estimation technique calle...