Logical effort based technology mapping

We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended to solve the loaddistribution problem for circuits with fanout. On average, benchmark circuits mapped using our approach are 25.39% faster than the solutions obtained from SIS.

• Type: Conference
• Year: 2004
• Where: ICCAD
• Authors: Shrirang K. Karandikar, Sachin S. Sapatnekar
• Keywords: Benchmark Circuits, Fanout-free Circuits, Hardware, ICCAD 2004, Library-based Technology Mapping