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ICCAD
2004
IEEE
94views Hardware» more  ICCAD 2004»
14 years 4 months ago
Timing macro-modeling of IP blocks with crosstalk
With the increase of design complexities and the decrease of minimal feature sizes, IP reuse is becoming a common practice while crosstalk is becoming a critical issue that must b...
Ruiming Chen, Hai Zhou
ICCAD
2004
IEEE
260views Hardware» more  ICCAD 2004»
14 years 4 months ago
On interactions between routing and detailed placement
The main goal of this paper is to develop deeper insights into viable placement-level optimization of routing. Two primary contributions are made. First, an experimental framework...
Devang Jariwala, John Lillis
ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
14 years 4 months ago
Accurate estimation of global buffer delay within a floorplan
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
ICCAD
2004
IEEE
95views Hardware» more  ICCAD 2004»
14 years 4 months ago
Low-power programmable routing circuitry for FPGAs
We propose two new FPGA routing switch designs that are programmable to operate in three different modes: highspeed, low-power or sleep. High-speed mode provides similar power an...
Jason Helge Anderson, Farid N. Najm
ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
14 years 4 months ago
Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems
In this paper, we propose a new technique for the combined voltage scaling of processors and communication links, taking into account dynamic as well as leakage power consumption....
Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Z...