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ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
14 years 4 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
ICCAD
2008
IEEE
129views Hardware» more  ICCAD 2008»
14 years 2 months ago
Path-RO: a novel on-chip critical path delay measurement under process variations
— As technology scales to 45nm and below, process variations will present significant impact on path delay. This trend makes the deviation between simulated path delay and actua...
Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Dat...
ICCAD
2008
IEEE
115views Hardware» more  ICCAD 2008»
14 years 4 months ago
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
- In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running...
Mohammad Ghasemazar, Massoud Pedram
ICCAD
2008
IEEE
106views Hardware» more  ICCAD 2008»
14 years 4 months ago
Process variability-aware transient fault modeling and analysis
– Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the...
Natasa Miskov-Zivanov, Kai-Chiang Wu, Diana Marcul...
ICCAD
2008
IEEE
89views Hardware» more  ICCAD 2008»
14 years 4 months ago
Temperature aware task sequencing and voltage scaling
Abstract—On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of syst...
Ramkumar Jayaseelan, Tulika Mitra