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ICCAD
2008
IEEE

Path-RO: a novel on-chip critical path delay measurement under process variations

14 years 5 months ago
Path-RO: a novel on-chip critical path delay measurement under process variations
— As technology scales to 45nm and below, process variations will present significant impact on path delay. This trend makes the deviation between simulated path delay and actual path delay in a manufactured chip more significant. In this paper, we propose a new onchip path delay measurement structure called path-based ring oscillator (Path-RO). The proposed method creates an oscillator from a targeted path for which it is used to measure path delay on-chip under the impact of process variations. To alleviate accuracy degradation caused by the architecture itself, a high-accuracy calibration process is presented. Through experimental results on Path-ROs inserted in ITC’99 b19 benchmark, we obtain path delay distribution under different process variations. The accuracy and efficiency of path delay measurement using Path-RO are also verified by comparing the results obtained from postlayout Hspice simulations.
Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Dat
Added 30 May 2010
Updated 30 May 2010
Type Conference
Year 2008
Where ICCAD
Authors Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta
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