In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
Wire bonding is the most popular method to connect signals between dies in System-in-Package (SiP) design nowadays. Pad assignment, which assigns inter-die signals to die pads so ...
Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang
As CMOS devices are scaled down into the nanometer regime, concerns about reliability are mounting. Instead of viewing nanoscale characteristics as an impediment, technologies suc...
Weikang Qian, Marc D. Riedel, Kia Bazargan, David ...