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ICCAD
2009
IEEE
144views Hardware» more  ICCAD 2009»
13 years 5 months ago
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton
ICCAD
2009
IEEE
92views Hardware» more  ICCAD 2009»
13 years 5 months ago
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
ICCAD
2009
IEEE
109views Hardware» more  ICCAD 2009»
13 years 5 months ago
Energy reduction for STT-RAM using early write termination
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
Ping Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang
ICCAD
2009
IEEE
154views Hardware» more  ICCAD 2009»
13 years 5 months ago
Pad assignment for die-stacking System-in-Package design
Wire bonding is the most popular method to connect signals between dies in System-in-Package (SiP) design nowadays. Pad assignment, which assigns inter-die signals to die pads so ...
Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang
ICCAD
2009
IEEE
87views Hardware» more  ICCAD 2009»
13 years 5 months ago
The synthesis of combinational logic to generate probabilities
As CMOS devices are scaled down into the nanometer regime, concerns about reliability are mounting. Instead of viewing nanoscale characteristics as an impediment, technologies suc...
Weikang Qian, Marc D. Riedel, Kia Bazargan, David ...