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ICCD
2001
IEEE
86views Hardware» more  ICCD 2001»
14 years 6 months ago
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement
Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aima...
ICCD
2001
IEEE
72views Hardware» more  ICCD 2001»
14 years 6 months ago
Linear Time Hierarchical Capacitance Extraction without Multipole Expansion
Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk...
ICCD
2001
IEEE
105views Hardware» more  ICCD 2001»
14 years 6 months ago
Timing Characterization of Dual-edge Triggered Flip-flops
A novel timing characterization for dual-edge triggered flip-flops is presented in this paper. This characterization takes into account the real overhead taken from the clock cycl...
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
14 years 6 months ago
Interconnect-centric Array Architectures for Minimum SRAM Access Time
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, Jame...
ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
14 years 6 months ago
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked...
Martin Saint-Laurent, Madhavan Swaminathan, James ...