Timing Characterization of Dual-edge Triggered Flip-flops

A novel timing characterization for dual-edge triggered flip-flops is presented in this paper. This characterization takes into account the real overhead taken from the clock cycle by the flip-flops. Our study shows the correctness of this new metrics when compared against data-to-output delay.

• Type: Conference
• Year: 2001
• Where: ICCD
• Authors: Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
• Keywords: Clock Cycle, Dual-edge Triggered Flip-flops, Hardware, ICCD 2001, Real Overhead