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ICCD
2001
IEEE
154views Hardware» more  ICCD 2001»
14 years 6 months ago
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
ICCD
2001
IEEE
84views Hardware» more  ICCD 2001»
14 years 6 months ago
Static Energy Reduction Techniques for Microprocessor Caches
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, S...
ICCD
2001
IEEE
77views Hardware» more  ICCD 2001»
14 years 6 months ago
Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State
This paper introduces minimal subset evaluation (MSE) as a way to reduce time spent on large-structure warm-up during the fastforwarding portion of processor simulations. Warm up ...
John W. Haskins Jr., Kevin Skadron
ICCD
2001
IEEE
112views Hardware» more  ICCD 2001»
14 years 6 months ago
Run-Time Execution of Reconfigurable Hardware in a Java Environment
We present tools that support the runtime execution of applications that mix software running on networks of workstations and reconfigurable hardware. We use JHDL to describe the ...
Laurie A. Smith King, Heather Quinn, Miriam Leeser...
ICCD
2001
IEEE
110views Hardware» more  ICCD 2001»
14 years 6 months ago
Low-Energy DSP Code Generation Using a Genetic Algorithm
This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm bas...
Markus Lorenz, Rainer Leupers, Peter Marwedel, Tho...