Design guidelines for low- and ultra low-power arithmetic units are presented. We analyze structures for addition in the energy-delay space to determine the most suitable for thes...
Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdz...
We present a scalable architectural approach which aims to simplify embedded software development by supporting key development tasks like debugging, tracing and monitoring. Our a...
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay...
In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to re...
Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T....