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ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
Transaction-level modeling (TLM) allows a designer to save functional verification effort during the modular refinement of an SoC by reusing the prior implementation of a module a...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper explores statistical simulation as a fast simulation technique for driving chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to ...