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ICS
1999
Tsinghua U.
14 years 1 months ago
1999
Tsinghua U.
A consistency protocol can be termed symmetric if all processors are treated identically when they access common resources. By contrast, asymmetric protocols usually assign a home...
ICS
1999
Tsinghua U.
14 years 1 months ago
1999
Tsinghua U.
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
ICS
1999
Tsinghua U.
14 years 1 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
ICS
1999
Tsinghua U.
14 years 1 months ago
1999
Tsinghua U.
The performance of irregular applications on modern computer systems is hurt by the wide gap between CPU and memory speeds because these applications typically underutilize multi-...
ICS
1999
Tsinghua U.
14 years 1 months ago
1999
Tsinghua U.
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...