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ISCA
2006
IEEE
133views Hardware» more  ISCA 2006»
14 years 3 months ago
TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
RAID architectures have been used for more than two decades to recover data upon disk failures. Disk failure is just one of the many causes of damaged data. Data can be damaged by...
Qing Yang, Weijun Xiao, Jin Ren
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
14 years 3 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
ISCAS
2006
IEEE
143views Hardware» more  ISCAS 2006»
14 years 3 months ago
Dynamic computation in a recurrent network of heterogeneous silicon neurons
Abstract—We describe a neuromorphic chip with a twolayer excitatory-inhibitory recurrent network of spiking neurons that exhibits localized clusters of neural activity. Unlike ot...
Paul Merolla, Kwabena Boahen
ISCAS
2006
IEEE
169views Hardware» more  ISCAS 2006»
14 years 3 months ago
An Address-Event Image Sensor Network
We discuss an imaging architecture for sensor pixel in the ALOHA signals an event when a certain amount network applications, that employs a 32 x 32 Address-Event of photons are re...
Thiago Teixeira, Eugenio Culurciello, Andreas G. A...
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
14 years 3 months ago
Silicon neurons that phase-lock
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
J. H. Wittig Jr., Kwabena Boahen
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