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IPPS
2000
IEEE
14 years 16 days ago
Three Dimensional VLSI-Scale Interconnects
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
Dennis W. Prather
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 16 days ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
VISUALIZATION
2000
IEEE
14 years 16 days ago
On-the-Fly rendering of losslessly compressed irregular volume data
Very large irregular-grid data sets are represented as tetrahedral meshes and may incur significant disk I/O access overhead in the rendering process. An effective way to allevia...
Chuan-Kai Yang, Tulika Mitra, Tzi-cker Chiueh
BMCBI
2004
159views more  BMCBI 2004»
13 years 8 months ago
Extractor for ESI quadrupole TOF tandem MS data enabled for high throughput batch processing
Background: Mass spectrometry based proteomics result in huge amounts of data that has to be processed in real time in order to efficiently feed identification algorithms and to e...
Andreas M. Boehm, Robert P. Galvin, Albert Sickman...
NN
2000
Springer
170views Neural Networks» more  NN 2000»
13 years 8 months ago
Synthetic brain imaging: grasping, mirror neurons and imitation
The article contributes to the quest to relate global data on brain and behavior (e.g. from PET, Positron Emission Tomography, and fMRI, functional Magnetic Resonance Imaging) to ...
Michael A. Arbib, Aude Billard, Marco Iacoboni, Er...