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IJCNN
2000
IEEE
14 years 17 days ago
Analog Hardware Implementation of the Random Neural Network Model
This paper presents a simple continuous analog hardware realization of the Random Neural Network (RNN) model. The proposed circuit uses the general principles resulting from the u...
Hossam Abdelbaki, Erol Gelenbe, Said E. El-Khamy
INFOVIS
2000
IEEE
14 years 17 days ago
Visualizing Massive Multi-Digraphs
We describe MGV, an integrated visualization and exploration system for massive multi-digraph navigation. MGV’s only assumption is that the vertex set of the underlying digraph ...
James Abello, Jeffrey L. Korn
IPPS
2000
IEEE
14 years 17 days ago
Enhancing NWS for Use in an SNMP Managed Internetwork
The Network Weather Service NWS is a distributed resource monitoring and utilization prediction system, employed as an aid to scheduling jobs in a metacomputing environment 9, 1...
Robert E. Busby Jr., Mitchell L. Neilsen, Daniel A...
ISCA
2000
IEEE
134views Hardware» more  ISCA 2000»
14 years 17 days ago
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on si...
Marcelo H. Cintra, José F. Martínez,...
ISCA
2000
IEEE
92views Hardware» more  ISCA 2000»
14 years 17 days ago
Trace preconstruction
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
Quinn Jacobson, James E. Smith