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    GLVLSI
    1998
    IEEE
    77views VLSI» more  GLVLSI 1998»
    Power Reducing Techniques for Clocked CMOS PLAs
    15 years 7 months ago
    Power Reducing Techniques for Clocked CMOS PLAs
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    Richard F. Hobson
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    GLVLSI
    1998
    IEEE
    114views VLSI» more  GLVLSI 1998»
    The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer
    15 years 7 months ago
    The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer
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    Inseop Lee, W. Kenneth Jenkins
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    102
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    GLVLSI
    1998
    IEEE
    94views VLSI» more  GLVLSI 1998»
    Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation
    15 years 7 months ago
    Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation
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    Muhammad M. Khellah, Mohamed I. Elmasry
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    79
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    GLVLSI
    1998
    IEEE
    84views VLSI» more  GLVLSI 1998»
    Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS
    15 years 7 months ago
    Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS
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    Jianping Lu, Sofiène Tahar
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    105
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    GLVLSI
    1998
    IEEE
    119views VLSI» more  GLVLSI 1998»
    A Methodology for High Level Power Estimation and Exploration
    15 years 7 months ago
    A Methodology for High Level Power Estimation and Exploration
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    Vamsi Krishna, N. Ranganathan
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