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8949
search results - page 49 / 1790
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GLVLSI
1998
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Power Reducing Techniques for Clocked CMOS PLAs
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Richard F. Hobson
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1998
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The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer
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Inseop Lee, W. Kenneth Jenkins
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1998
IEEE
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Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation
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Muhammad M. Khellah, Mohamed I. Elmasry
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1998
IEEE
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Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS
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Jianping Lu, Sofiène Tahar
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1998
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A Methodology for High Level Power Estimation and Exploration
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Vamsi Krishna, N. Ranganathan
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