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120

APSEC
2000
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Building Formal Models for Software Requirements

15 years 8 months ago

Building Formal Models for Software Requirements

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Axel van Lamsweerde

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94

APSEC
2000
IEEE

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Translating descriptions of a viewpoint among different representations

15 years 8 months ago

Translating descriptions of a viewpoint among different representations

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Nigel Stanger

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98

ASYNC
2000
IEEE

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Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL

15 years 8 months ago

Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL

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Ivan Blunno, Luciano Lavagno

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115

ASYNC
2000
IEEE

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Formal Verification of Safety Properties in Timed Circuits

15 years 8 months ago

Formal Verification of Safety Properties in Timed Circuits

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Marco A. Peña, Jordi Cortadella, Enric Past...

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81

ATS
2000
IEEE

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Testing in the Fourth Dimension

15 years 8 months ago

Testing in the Fourth Dimension

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Vishwani D. Agrawal, Kwang-Ting Cheng

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