Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
PDF Tools
Image Tools
Text Tools
OCR Tools
Symbol and Emoji Tools
On-screen Keyboard
Latex Math Equation to Image
Smart IPA Phonetic Keyboard
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
16
search results - page 4 / 4
»
isca 1996
Sort
relevance
views
votes
recent
update
View
thumb
title
123
click to vote
DAC
1996
ACM
129
views
Computer Architecture
»
more
DAC 1996
»
Optimal Clock Skew Scheduling Tolerant to Process Variations
15 years 7 months ago
Download
www.ece.rochester.edu
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
José Luis Neves, Eby G. Friedman
claim paper
Read More »
« Prev
« First
page 4 / 4
Last »
Next »