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ISCAS
2006
IEEE
99views Hardware» more  ISCAS 2006»
14 years 2 months ago
High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor
— By implementing an FPGA-based simulator, we investigate the performance of high-rate quasi-cyclic (QC) LDPC codes for the magnetic recording channel at very low sector error ra...
Hao Zhong, Tong Zhang, Erich F. Haratsch
ISCAS
2006
IEEE
105views Hardware» more  ISCAS 2006»
14 years 2 months ago
A CMOS contact imager for locating individual cells
— We describe the design of a contact imager for applications in lab-on-a-chip systems, such as sample preparation and manipulation and monitoring of cells. This is a challenging...
Honghao Ji, David Sander, A. Haas, Pamela Abshire
ISCAS
2006
IEEE
90views Hardware» more  ISCAS 2006»
14 years 2 months ago
Quality-biased rate allocation for compound image coding with block classification
- In this paper, we propose a novel rate allocation method for compound image coding using Quality-biased Rate-Distortion Optimization (QRDO) technique to enhance visual quality. T...
Dong Liu, Wenpeng Ding, Yuwen He, Feng Wu
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
14 years 2 months ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman
ISCAS
2006
IEEE
100views Hardware» more  ISCAS 2006»
14 years 2 months ago
Decoders for low-density parity-check convolutional codes with large memory
— Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and dec...
Stephen Bates, L. Gunthorpe, Ali Emre Pusane, Zhen...