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ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
the following cost functions: In this paper, learning rules are proposed for simultaneous corn- GI(U) = tr{(UTU)(UTBU)-lD, (la) putation of minor eigenvectors of a covariance matri...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
ISCA
2006
IEEE
13 years 8 months ago
2006
IEEE
Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has exa...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...