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IJFCS
1998
67views more  IJFCS 1998»
13 years 7 months ago
Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits
Directed acyclic graphs (dags) are often used to model circuits. Path lengths in such dags represent circuit delays. In the vertex splitting problem, the objective is to determine...
Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni
ISCA
2009
IEEE
158views Hardware» more  ISCA 2009»
14 years 2 months ago
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
Carlos Madriles, Pedro López, Josep M. Codi...
ISCA
2010
IEEE
163views Hardware» more  ISCA 2010»
14 years 21 days ago
WiDGET: Wisconsin decoupled grid execution tiles
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
Yasuko Watanabe, John D. Davis, David A. Wood
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 21 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
237views Hardware» more  ISCA 2010»
13 years 6 months ago
High performance cache replacement using re-reference interval prediction (RRIP)
Practical cache replacement policies attempt to emulate optimal replacement by predicting the re-reference interval of a cache block. The commonly used LRU replacement policy alwa...
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely J...