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ISQED
2008
IEEE
85views Hardware» more  ISQED 2008»
14 years 5 months ago
A Statistic-Based Approach to Testability Analysis
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulati...
Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen
TC
2008
13 years 10 months ago
Low-Transition Test Pattern Generation for BIST-Based Applications
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
ISCA
2008
IEEE
112views Hardware» more  ISCA 2008»
14 years 5 months ago
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
Onur Mutlu, Thomas Moscibroda
ISCA
2008
IEEE
142views Hardware» more  ISCA 2008»
14 years 5 months ago
Improving NAND Flash Based Disk Caches
Flash is a widely used storage device that provides high density and low power, appealing properties for general purpose computing. Today, its usual application is in portable spe...
Taeho Kgil, David Roberts, Trevor N. Mudge
ISCA
2008
IEEE
139views Hardware» more  ISCA 2008»
14 years 5 months ago
Atom-Aid: Detecting and Surviving Atomicity Violations
Writing shared-memory parallel programs is error-prone. Among the concurrency errors that programmers often face are atomicity violations, which are especially challenging. They h...
Brandon Lucia, Joseph Devietti, Karin Strauss, Lui...