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ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 8 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
ISCA
2010
IEEE
163views Hardware» more  ISCA 2010»
14 years 2 months ago
WiDGET: Wisconsin decoupled grid execution tiles
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
Yasuko Watanabe, John D. Davis, David A. Wood
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 2 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 2 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
ISCA
2010
IEEE
210views Hardware» more  ISCA 2010»
14 years 2 months ago
An intra-chip free-space optical interconnect
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless s...
Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun ...