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ISCAS
2005
IEEE
148views Hardware» more  ISCAS 2005»
14 years 2 months ago
. Analog slice turbo decoding
— This paper presents the design of an analog turbo decoder for DVB-RCS-like applications using a slice architecture. The constituent decoders for different frame lengths are mad...
Matthieu Arzel, Cyril Lahuec, Fabrice Seguin, Davi...
ISCAS
2005
IEEE
98views Hardware» more  ISCAS 2005»
14 years 2 months ago
An ultrasonic filterbank with spiking neurons
—To support our ongoing work in modeling bat echolocation, a binaural, ultrasonic cochlea-like filter bank has been designed with moderate quality (Q) factor (as high as 65) with...
Timothy K. Horiuchi, Hisham Abdalla
ISCAS
2005
IEEE
142views Hardware» more  ISCAS 2005»
14 years 2 months ago
Multichannel SVD-based image de-noising
: - In this paper, we propose a multichannel SVD-based image de-noising algorithm. The IntDCT is employed to decorrelate the image into sixteen subbands. The SVD is then applied to...
Yodchanan Wongsawat, K. R. Rao, Soontorn Oraintara
ISCAS
2005
IEEE
134views Hardware» more  ISCAS 2005»
14 years 2 months ago
Heap charge pump optimisation by a tapered architecture
- The heap charge pump represents an attractive voltage multiplier scheme in integrated circuits where only low-voltage devices are available. This paper presents a performance opt...
R. Arona, Edoardo Bonizzoni, Franco Maloberti, Gui...
ISCAS
2005
IEEE
121views Hardware» more  ISCAS 2005»
14 years 2 months ago
SET and RESET pulse characterization in BJT-selected phase-change memories
- This paper presents program pulse characterization in an 8-Mb BJT-selected Phase-Change Memory test chip. Experimental results of the impact of the bit-line resistance over progr...
Ferdinando Bedeschi, Edoardo Bonizzoni, Giulio Cas...