Process related variations are considered a major concern in emerging sub-65nm technologies. In this paper, we investigate the impact of process variations on different types of c...
In this paper, we propose a generalized block structure-preserving reduced order interconnect macromodeling method (BSPRIM). Our approach extends structure-preserving model order ...
Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fa...
Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significa...
Juan Pablo Martinez Brito, Hamilton Klimach, Sergi...
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
According to the current trend of increasing variations in process technologies and thus in performance, the conservative worst-case design will not work since design margins can ...