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ISSS
1996
IEEE
123views Hardware» more  ISSS 1996»
14 years 3 months ago
Memory Organization for Improved Data Cache Performance in Embedded Processors
Code generation for embedded processors creates opportunities for several performance optimizations not applicable for traditional compilers. We present techniques for improving d...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
ISSS
1996
IEEE
103views Hardware» more  ISSS 1996»
14 years 3 months ago
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
Guido Araujo, Ashok Sudarsanam, Sharad Malik
ISSS
1996
IEEE
134views Hardware» more  ISSS 1996»
14 years 3 months ago
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
An address generation and optimization environment (ADOPT) for distributed memory architectures, is presented. ADOPT is oriented to minimize the area overhead introduced by the us...
Miguel Miranda, Francky Catthoor, Martin Janssen, ...
ISSS
1996
IEEE
114views Hardware» more  ISSS 1996»
14 years 3 months ago
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
In this paper we present the problem of flow graph balancing for minimizingthe required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cy...
Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, ...
ISSS
1996
IEEE
102views Hardware» more  ISSS 1996»
14 years 3 months ago
Throughput Optimization in Disk-Based Real-Time Application Specific Systems
Traditionally, application specific computations have been focusing on numerically intensive data manipulation. Modern communications and DSP applications, such as WWW, interactiv...
Stephen Docy, Inki Hong, Miodrag Potkonjak