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ISPASS
2007
IEEE
14 years 4 months ago
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...
Wangyuan Zhang, Xin Fu, Tao Li, José A. B. ...
INFOCOM
2006
IEEE
14 years 3 months ago
MobiStream: Error-Resilient Video Streaming in Wireless WANs Using Virtual Channels
—We present MobiStream— a video streaming system that exploits the perceptual value in video content and the characteristics of the link layer and physical layer channels to en...
Rajiv Chakravorty, Suman Banerjee, Samrat Ganguly
CF
2006
ACM
14 years 3 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley
ICPPW
2005
IEEE
14 years 3 months ago
Speculative Parallel Threading Architecture and Compilation
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
Xiao-Feng Li, Zhao-Hui Du, Chen Yang, Chu-Cheow Li...
MICRO
2005
IEEE
110views Hardware» more  MICRO 2005»
14 years 3 months ago
Scalable Store-Load Forwarding via Store Queue Index Prediction
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
Tingting Sha, Milo M. K. Martin, Amir Roth