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ITC
2003
IEEE
145views Hardware» more  ITC 2003»
14 years 3 months ago
MEMS Manufacturing Testing: An Accelerometer Case Study
Electrical testing of MicroElectroMechanical Systems (MEMS) can take on many different forms including wafer probing, electrical trimming, final test at temperatures, engineering ...
Theresa Maudie, Alex Hardt, Rick Nielsen, Dennis S...
MICRO
2003
IEEE
128views Hardware» more  MICRO 2003»
14 years 3 months ago
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
Stefanos Kaxiras, Georgios Keramidas
MICRO
2003
IEEE
132views Hardware» more  MICRO 2003»
14 years 3 months ago
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasa...
MICRO
2003
IEEE
135views Hardware» more  MICRO 2003»
14 years 3 months ago
Generational Cache Management of Code Traces in Dynamic Optimization Systems
A dynamic optimizer is a runtime software system that groups a program’s instruction sequences into traces, optimizes those traces, stores the optimized traces in a softwarebase...
Kim M. Hazelwood, Michael D. Smith
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 3 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood