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IPPS
2006
IEEE
14 years 3 months ago
MegaProto/E: power-aware high-performance cluster with commodity technology
In our research project named “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, we have been developing a prototype cluster not based on ASIC or FPGA...
Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, H...
IPPS
2006
IEEE
14 years 3 months ago
High-performance computing in remotely sensed hyperspectral imaging: the Pixel Purity Index algorithm as a case study
The incorporation of last-generation sensors to airborne and satellite platforms is currently producing a nearly continual stream of high-dimensional data, and this explosion in t...
Antonio Plaza, David Valencia, Javier Plaza
ISCA
2006
IEEE
133views Hardware» more  ISCA 2006»
14 years 3 months ago
TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
RAID architectures have been used for more than two decades to recover data upon disk failures. Disk failure is just one of the many causes of damaged data. Data can be damaged by...
Qing Yang, Weijun Xiao, Jin Ren
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 3 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 3 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
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