Sciweavers

1709 search results - page 329 / 342
» networks 2000
Sort
View
CGO
2007
IEEE
14 years 3 months ago
Microarchitecture Sensitive Empirical Models for Compiler Optimizations
This paper proposes the use of empirical modeling techniques for building microarchitecture sensitive models for compiler optimizations. The models we build relate program perform...
Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. S...
ICC
2007
IEEE
170views Communications» more  ICC 2007»
14 years 3 months ago
Policy-Based QoS-Aware Packet Scheduling for CDMA 1x Ev-DO
— CDMA 1x Ev-DO is an evolution of the CDMA2000 3G wireless standard to enable high rate packet data services up to 2.4Mbps in Rev 0, 3.1Mbps in Rev A, and 4.9Mbps in Rev B. To s...
Jinho Hwang, M. Tamer Refaei, Hyeong-Ah Choi, Jae-...
MICRO
2007
IEEE
167views Hardware» more  MICRO 2007»
14 years 2 months ago
Informed Microarchitecture Design Space Exploration Using Workload Dynamics
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
Chang-Burm Cho, Wangyuan Zhang, Tao Li
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 2 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
ASPLOS
2004
ACM
14 years 2 months ago
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...