—Circuit-switched networks can significantly lower the communication latency between processor cores, when compared to packet-switched networks, since once circuits are set up, ...
Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H....
—Using analytical and simulation results, this paper presents comparative analyses between network on chip and shared-bus AMBA using real application traffic with MPEG-2 video d...
Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-H...
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the perf...
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu ...