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148
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
166
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Logic synthesis has made impressive progress in the last decade and has pervaded digital design replacing almost universally manual techniques. A remarkable exception is computer ...
145
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Physical synthesis optimizations and engineering change orders typically change the locations of cells, resize cells or add more cells to the design after global placement. Unfort...
161
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
170
Voted
ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...