Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling

This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constraints have led microprocessor designers to incorporate aggressive power saving techniques such as clock-gating, that place a significant burden on the power delivery network. While the application of extensive clock-gating can effectively reduce power consumption, unfortunately, it can also induce large inductive noise (di/dt), resulting in signal integrity and reliability issues. To combat these problems, processors are usually designed for the worst-case current consumption scenario using adequate supply voltage and decoupling capacitances. To tackle high-frequency inductive noise and potential IR drops, we propose a novel design methodology that integrates microarchitectural profiling feedback into the floorplanning process. We present two microarchitectural metrics to quantify the noise susceptibility of ...

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee
• Keywords: ASPDAC 2007, Hardware, Inductive Noise, Power Pins, Stringent Power Constraints