Convolutional network-error correcting codes (CNECCs) are known to provide error correcting capability in acyclic instantaneous networks within the network coding paradigm under sm...
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
This is the second participation of Institute of Statistical Studies and Research (ISSR) group in CLEF 2010-Medical image retrieval track. This paper describes our experiments in m...