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ICECCS
2010
IEEE
219views Hardware» more  ICECCS 2010»
13 years 7 months ago
Comparison of Six Ways to Extend the Scope of Cheddar to AADL v2 with Osate
Abstract—Cheddar is a framework dedicated to the specification of real-time schedulers, and to their analysis by simulation. It is developed in Ada. Some parts of its modular ar...
Mickaël Kerboeuf, Alain Plantec, Frank Singho...
EUROPAR
2010
Springer
13 years 7 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 7 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
CORR
2010
Springer
208views Education» more  CORR 2010»
13 years 7 months ago
Bounded Model Checking of Multi-threaded Software using SMT solvers
The transition from single-core to multi-core processors has made multi-threaded software an important subject in computer aided verification. Here, we describe and evaluate an ex...
Lucas Cordeiro, Bernd Fischer 0002
CORR
2010
Springer
152views Education» more  CORR 2010»
13 years 7 months ago
Neuroevolutionary optimization
Temporal difference methods are theoretically grounded and empirically effective methods for addressing reinforcement learning problems. In most real-world reinforcement learning ...
Eva Volná