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APCCAS
2002
IEEE
138views Hardware» more  APCCAS 2002»
14 years 2 months ago
A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter
This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as ...
A. Tamtrakarn, N. Wongkomet
ASYNC
2002
IEEE
112views Hardware» more  ASYNC 2002»
14 years 2 months ago
A Negative-Overhead, Self-Timed Pipeline
This paper presents a novel variation of wave pipelining that we call “surfing.” In previous wave pipelined designs, timing uncertainty grows monotonically as events propagat...
Mark R. Greenstreet, Brian D. Winters
ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
14 years 2 months ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim
ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
14 years 2 months ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...
CA
2002
IEEE
14 years 2 months ago
Conversational Virtual Character for the Web
Talking virtual characters are graphical simulations of real or imaginary persons capable of human-like behaviour, most importantly talking and gesturing. Coupled with artificial ...
Karlo Smid, Igor S. Pandzic