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SIGARCH
2008
96views more  SIGARCH 2008»
13 years 10 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
IJRR
2007
100views more  IJRR 2007»
13 years 10 months ago
Exactly Sparse Extended Information Filters for Feature-based SLAM
Recent research concerning the Gaussian canonical form for Simultaneous Localization and Mapping (SLAM) has given rise to a handful of algorithms that attempt to solve the SLAM sc...
Matthew Walter, Ryan Eustice, John J. Leonard
IJSNET
2007
169views more  IJSNET 2007»
13 years 10 months ago
ART: an asymmetric and reliable transport mechanism for wireless sensor networks
: Many applications developed for wireless sensor networks (WSNs) demand for Reliable communication service, since majority of these applications are event-critical applications. T...
Nurcan Tezcan, Wenye Wang
TCAD
2008
136views more  TCAD 2008»
13 years 10 months ago
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
TCAD
2008
89views more  TCAD 2008»
13 years 10 months ago
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning
We present in this paper a new interconnect-driven multilevel floorplanner, called interconnect-driven multilevelfloorplanning framework (IMF), to handle large-scale buildingmodule...
Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin