— Scaling down the voltage levels of the processing elements (PEs) in a Network-on-Chip (NoC) can significantly reduce the computation energy consumption with an overhead of the...
— A distributed on-chip decoupling capacitor network is proposed in this paper to replace one large capacitor. A system of distributed on-chip decoupling capacitors is shown to p...
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
— Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...