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TCAD
1998
125views more  TCAD 1998»
13 years 7 months ago
Test-point insertion: scan paths through functional logic
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
TCAD
1998
91views more  TCAD 1998»
13 years 7 months ago
Cost-free scan: a low-overhead scan path design
Conventional scan design imposes considerable area and delay overhead by using larger scan ip- ops and additional scan wires without utilizing the functionality of the combinatio...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Ti...
TCAD
1998
125views more  TCAD 1998»
13 years 7 months ago
BDD-based synthesis of extended burst-mode controllers
Abstract—We examine the implications of a new hazard-free combinational logic synthesis method [1], which generates multiplexor-based networks from binary decision diagrams (BDDs...
Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas ...
TCAD
2002
145views more  TCAD 2002»
13 years 7 months ago
Automatic generation of synthetic sequential benchmark circuits
The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist gr...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
TCAD
1998
114views more  TCAD 1998»
13 years 7 months ago
Behavioral optimization using the manipulation of timing constraints
— We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG’s) during the high-level synthesis of data-pathinten...
Miodrag Potkonjak, Mani B. Srivastava