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ISPAN
2002
IEEE
14 years 3 months ago
Automatic Processor Lower Bound Formulas for Array Computations
In the directed acyclic graph (dag) model of algorithms, consider the following problem for precedence-constrained multiprocessor schedules for array computations: Given a sequenc...
Peter R. Cappello, Ömer Egecioglu
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
14 years 3 months ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 3 months ago
Security-Driven Exploration of Cryptography in DSP Cores
With the popularity of wireless communication devices a new important dimension of embedded systems design has arisen, that of security. This paper presents for the first time des...
Catherine H. Gebotys
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 3 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
ITC
2002
IEEE
114views Hardware» more  ITC 2002»
14 years 3 months ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...