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GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundari...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
ICRA
2005
IEEE
14 years 1 months ago
2005
IEEE
– We describe in detail the behavior of an inhibitory Central Pattern Generator (CPG) network for robot control. A four-neuron, mutual inhibitory network forms the basic coordina...